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MGP3006X6

GHz PLL with I2C Bus and Four Chip Addresses

Infineon Technologies 

MGP 3006X6

I2C Bus Interface

Data are exchanged between the processor and the PLL on the I2C Bus.

SCL, SDA

The clock is generated by the processor (input SCL), while pin SDA works

as an input or output depending on the direction of the data (open

collector; external pull-up resistor). Both inputs have hysteresis and a

low-pass characteristic, which enhances the noise immunity of the I2C

Bus.

The data from the processor pass through an I2C Bus control. Depending

on their function the data are subsequently stored in registers. If the bus

is free, both lines will be in the marking state (SDA, SCL are high). Each

telegram begins with the start condition and ends with the stop condition.

Start condition: SDA goes low, while SCL remains high. Stop condition:

SDA goes high while SCL remains high. All further information transfer

takes place during SCL = low, and the data is forwarded to the control

logic on the positive clock edge.

The table “bit allocation” should be referred to in the following paragraph.

All telegrams are transmitted byte-by-byte, followed by a ninth clock

pulse, during which the control logic returns the SDA-line to low

(acknowledge condition). The first byte is comprised of seven address

bits. These are used by the processor to select the PLL from several

peripheral components (chip select). The eighth bit is always low.

In the data portion of the telegram the first bit of the first or third data byte

determines whether a divider ratio or control information is to follow. In

each case the second byte of the same data type or a stop condition has

to follow the first byte.

VS, GND

When the supply voltage is applied a power-on reset circuit prevents the

PLL from setting the SDA-line to low, which would block the bus.

Semiconductor Group

3

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