M12L128324A-7BG2E Ver la hoja de datos (PDF) - [Elite Semiconductor Memory Technology Inc.

Número de pieza

componentes Descripción

Fabricante

M12L128324A-7BG2E

1M x 32 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

(Preliminary)

M12L128324A (2E)

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1) Clock Suspended During Write (BL=4)

CLK

2) Clock Suspended During Read (BL=4)

CMD

WR

RD

CKE

Internal

CLK

DQ(CL2)

Masked by CKE

D0 D1

D2 D3

Q0 Q1

Q2

Q3

DQ(CL3)

D0 D1

D2 D3

Q0 Q1

Q2

Q3

Not Written

Suspended Dout

2. DQM Operation

CLK

1)Write Mask (BL=4)

CMD

WR

DQM

DQ(CL2)

D0 D1

Masked b y DQ M

D3

DQ(CL3)

D0 D1

D3

DQM to Data-in Mask=0

2)Read Mask (BL=4)

RD

Masked by DQM

Hi-Z

Q0

Q2 Q3

Hi-Z

Q1 Q2 Q3

DQM to Data-out Mask=2

3)DQM with clcok suspended (Full Page Read)

*Note2

CLK

CMD

RD

CKE

Internal

CLK

DQM

DQ(CL2)

DQ(CL3)

Hi-Z

Q0

Q2

Hi-Z

Q1

Hi-Z

Q4

Hi-Z

Q3

Hi-Z

Hi-Z

Q6 Q7 Q8

Q5 Q6 Q7

*Note: 1. CKE to CLK disable/enable = 1CLK.

2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.

3. DQM masks both data-in and data-out.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2011

Revision: 0.1

16/44

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