Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (83940DKILF)
ICS83940DI
DATA SHEET
General Description
The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
Block Diagram
CLK_SEL Pulldown
PCLK Pulldown
nPCLK Pullup/Pulldown
0
LVCMOS_CLK Pulldown
1
18
Q0:Q17
Features
• Eighteen LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• For functional replacement part for 83940DKILF use 87016i
Pin Assignments
32 31 30 29 28 27 26 25
GND 1
24 Q6
GND 2
23 Q7
LVCMOS_CLK 3
22 Q8
CLK_SEL 4
PCLK 5
ICS83940DI
21 VDD
20 Q9
nPCLK 6
19 Q10
VDD 7
18 Q11
VDDO 8
17 GND
9 10 11 12 13 14 15 16
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
32 31 30 29 28 27 26 25
1
24 Q6
2
23 Q7
3
22 Q8
4 ICS83940DI 21 VDD
5
20 Q9
6
19 Q10
7
18 Q11
8
17 GND
9 10 11 12 13 14 15 16
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS83940DYI REVISION C May 19, 2016
1
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