DS2182 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

DS2182

T1 Line Monitor Chip

Maxim Integrated 

RCR1: Receive Control Register 1

MSB

ARC

OOF1

OOF2

ACR

DS2182A T1 Line Monitor Chip

SYNCC

SYNCT

SYNCE

LSB

RESYNC

NAME

ARC

OOF1

OOF2

ACR

SYNCC

SYNCT

SYNCE

RESYNC

POSITION

RCR1.7

RCR1.6

RCR1.5

RCR1.4

RCR1.3

RCR1.2

RCR1.1

RCR1.0

FUNCTION

Auto Resync Criteria

1 = resync on OOF event only

0 = resync on OOF event or Receive Carrier Loss (RCL)

Out-of-Frame 1. OOF event description. Valid when RCR1.5 is cleared.

1 = 2 out of 5 frame bits (FT or FPS) in error

0 = 2 out of 4 frame bits (FT or FPS) in error

Out-of-Frame 2. OOF event description.

1 = 2 out of 6 frame bits (FT or FPS) in error

0 = follow OOF event described in RCR1.6

Auto Counter Reset. When set, all four of the counters are reset to 0 when

read.

Sync Criteria. Determines the type of algorithm used by the receive

synchronizer; differs for each frame mode.

193S Framing (RCR2.4 = 0)

0 = synchronize to frame boundaries using FT pattern, then search for

multiframe by using FS

1 = cross couple FT and FS patterns in sync algorithm

193E Framing (RCR2.4 = 1)

0 = normal sync (uses FPS only)

1 = validate new alignment with CRC before declaring sync

Sync Time

1 = validate 24 consecutive F-bits before declaring sync

0 = validate 10 consecutive F-bits before declaring sync

Sync Enable. If clear, the DS2182A automatically begins a resync if the

conditions described in RCR1.7 are met. If set, no auto resync occurs.

Resync. When toggled low to high, the DS2182A initiates a resync

immediately. The bit must be cleared and set again for subsequent resyncs.

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