DS2182 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

DS2182

T1 Line Monitor Chip

Maxim Integrated 

DS2182A T1 Line Monitor Chip

Sync Enable (RCR1.1)

When RCR1.1 is cleared, the receiver initiates automatic resync if an OOF event occurs or if carrier loss (192

consecutive 0’s) occurs (depends on RCR1.7). When RCR1.1 is set, the automatic resync circuitry is disabled. In

this case, resync can only be initiated by setting RCR1.0 to 1 or externally transitioning RST from low to high. Note

that using RST to initiate a resync resets the output timing while RST is low; use of RCR1.1 does not affect the

output timing until the new alignment is located.

Resync (RCR1.0)

A 0-to-1 transition of RCR1.0 causes the synchronizer to search for the framing pattern sequence immediately,

regardless of the internal sync status. To initiate another resync command, this bit must be cleared and then set

again.

RCR2: Receive Control Register 2

MSB

—

—

BVCRF

FM

SFYEL

B8ZS

—

LSB

—

NAME

—

—

BVCRF

FM

SFYEL

B8ZS

—

—

POSITION

RCR2.7

RCR2.6

RCR2.5

RCR2.4

RCR2.3

RCR2.2

RCR2.1

RCR2.10

FUNCTION

Reserved; must be 0 for proper operation

Reserved; must be 0 for proper operation

Bipolar Violation Count Register Function Select

0 = do not count excessive 0’s

1 = count excessive 0’s

Frame Mode

1 = Extended Superframe (193E, 24 frames per Superframe)

0 = Superframe (193S or D4, 12 frames per Superframe)

SF Yellow Mode Select

1 = 1 in the S-bit position of frame 12

0 = 0 in bit 2 of all channels

Bipolar Eight-Zero Substitution

1 = B8ZS enabled

0 = B8ZS disabled

Reserved; must be 0 for proper operation

Reserved; must be 0 for proper operation

15 of 26

Share Link: