DS3254 Ver la hoja de datos (PDF) - Maxim Integrated
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DS3254 Datasheet PDF : 71 Pages
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DS3251/DS3252/DS3253/DS3254
7. REGISTER DESCRIPTIONS
When the DS325x is configured in either of the two CPU bus modes (HW = 0), the registers shown in Table 7-A
are accessible through the CPU bus interfaces. All registers for the LIU ports are forced to their default values
during an internal power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit high forces all
registers for that LIU to their default values. All register bits marked “—” must be written 0 and ignored when read.
The TEST registers must be left at their reset value of 00h for normal operation.
On the DS3253, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.
Reads from LIU 4 address space return all zeros. On the DS3252, address line A5 is not present, limiting the
address space to the LIU 1 and LIU 2 registers. On the DS3251, address lines A5 and A4 are not present, limiting
the address space to the LIU 1 registers.
Table 7-A. Register Map
ADDRESS
REGISTER
BIT 7
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h–0Fh
GCR1
TCR1
RCR1
SR1
SRL1
SRIE1
RCVL1
RCVH1
CACR
Test Registers
E3M
JAL[1]
ITU
—
JAFL
JAFIE
RCV[7]
RCV[15]
T3MOE
—
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h–1Fh
GCR2
TCR2
RCR2
SR2
SRL2
SRIE2
RCVL2
RCVH2
unused
Test Registers
E3M
JAL[1]
ITU
—
JAFL
JAFIE
RCV[7]
RCV[15]
—
—
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h–2Fh
GCR3
TCR3
RCR3
SR3
SRL3
SRIE3
RCVL3
RCVH3
unused
Test Registers
E3M
JAL[1]
ITU
—
JAFL
JAFIE
RCV[7]
RCV[15]
—
—
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h–3Fh
GCR4
TCR4
RCR4
SR4
SRL4
SRIE4
RCVL4
RCVH4
unused
Test Registers
E3M
JAL[1]
ITU
—
JAFL
JAFIE
RCV[7]
RCV[15]
—
—
BIT 6
STS
TBIN
RBIN
—
JAEL
JAEIE
RCV[6]
RCV[14]
E3MOE
—
STS
TBIN
RBIN
—
JAEL
JAEIE
RCV[6]
RCV[14]
—
—
STS
TBIN
RBIN
—
JAEL
JAEIE
RCV[6]
RCV[14]
—
—
STS
TBIN
RBIN
—
JAEL
JAEIE
RCV[6]
RCV[14]
—
—
BIT 5
LIU 1
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
STMOE
—
LIU 2
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
—
LIU 3
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
—
LIU 4
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
—
BIT 4
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
BIT 3
BIT 2
BIT 1
BIT 0
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
—
TTS
TLBO
RTS
RMON
—
RLOL
RCVL
RLOLL
RCVIE
RLOLIE
RCV[2]
RCV[1]
RCV[10] RCV[9]
AMCSEL[1] AMCSEL[0]
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
AMCEN
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
—
Note 1: Underlined bits are read-only; all other bits are read-write.
Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4). The register names are hyperlinks to the register descriptions.
Note 3: The bit names are the same for each LIU register set.
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