ISL29028 Ver la hoja de datos (PDF) - Renesas Electronics

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ISL29028

Low Power Ambient Light and Proximity Sensor with Intelligent Interrupt and Sleep Modes

Renesas Electronics 

ISL29028

Electrical Specifications VDD = 3.0V, TA = +25°C, REXT = 499k1% tolerance. (Continued)

PARAMETER

DESCRIPTION

CONDITION

MIN TYP MAX UNIT

IIRDR_LEAK IRDR Leakage Current

PROX_EN = 0; VDD = 3.63V (Note 8)

0.001 1

µA

VIRDR Acceptable Voltage Range on IRDR Pin

Register bit PROX_DR = 0

0.5

4.3 V

tPULSE Net IIRDR On Time Per PROX Reading

100

µs

VREF

FI2C

VI2C

Voltage of REXT Pin

I2C Clock Rate Range

Supply Voltage Range for I2C Interface

0.51

V

400 kHz

1.7

3.63 V

VIL

SCL and SDA Input Low Voltage

0.55 V

VIH

SCL and SDA Input High Voltage

1.25

V

ISDA

SDA Current Sinking Capability

VOL = 0.4V

35

mA

IINT

INT Current Sinking Capability

VOL = 0.4V

35

mA

PSRRIRDR (IIRDR)/(VIRDR)

PROX_DR = 0; VIRDR = 0.5V to 4.3V

4

mA/V

NOTES:

6. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light

source of the same lux level.

7. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.

8. Ability to guarantee IIRDR leakage of ~1nA is limited by test hardware.

9. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.

I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499k 1%

tolerance (Note 10).

PARAMETER

DESCRIPTION

VI2C

Supply Voltage Range for I2C Interface

fSCL

SCL Clock Frequency

VIL

SCL and SDA Input Low Voltage

VIH

SCL and SDA Input High Voltage

Vhys

Hysteresis of Schmitt Trigger Input

VOL

Low-level output voltage (open-drain) at

4mA sink current

CONDITION

MIN

1.7

1.25

0.05VDD

TYP MAX UNIT

3.63 V

400 kHz

0.55 V

V

V

0.4 V

Ii

Input Leakage for each SDA, SCL pin

tSP

Pulse Width of Spikes that must be

Suppressed by the Input Filter

-10

10 µA

50 ns

tAA

SCL Falling Edge to SDA Output Data Valid

Ci

Capacitance for each SDA and SCL pin

tHD:STA Hold Time (Repeated) START Condition

After this period, the first clock pulse

600

is generated

900 ns

10 pF

ns

tLOW

LOW Period of the SCL clock

Measured at the 30% of VDD

1300

ns

crossing

tHIGH

tSU:STA

HIGH period of the SCL Clock

Set-up Time for a Repeated START

Condition

600

ns

600

ns

tHD:DAT

tSU:DAT

tR

Data Hold Time

Data Set-up Time

Rise Time of both SDA and SCL Signals

(Note 11)

30

ns

100

ns

20 + 0.1xCb

ns

FN6780 Rev 2.00

November 4, 2011

Page 4 of 16

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