ISL8502A Ver la hoja de datos (PDF) - Renesas Electronics
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ISL8502A Datasheet PDF : 20 Pages
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ISL8502A
Increasing the value of inductance reduces the ripple current and
voltage. However, the large inductance values reduce the
converter response time to a load transient.
One of the parameters limiting converter response to a load
transient is the time required to change the inductor current.
Given a sufficiently fast control loop design, the ISL8502A
provides either 0% or 100% duty cycle in response to a load
transient. The response time is the time required to slew the
inductor current from an initial current value to the transient
current level. During this interval, the difference between the
inductor current and the transient current level must be
supplied by the output capacitor. Minimizing the response time
can minimize the output capacitance required.
The response time to a transient is different for the application of
load and the removal of load. Equation 9 gives the approximate
response time interval for application and removal of a transient
load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
(EQ. 9)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst-case response
time can be either at the application or removal of load. Be sure
to check both of these equations at the minimum and maximum
output levels for the worst-case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high-frequency decoupling, and bulk capacitors to supply the
current needed each time the upper MOSFET turns on. Place the
small ceramic capacitors physically close to the MOSFETs and
between the drain of the upper MOSFET and the source of the
lower MOSFET.
The important parameters for bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. Their voltage rating should be at least 1.25x greater than
the maximum input voltage, while a voltage rating of 1.5x is a
conservative guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately one-half the DC load current.
The maximum RMS current through the input capacitors can be
closely approximated using Equation 10:
V---V--O--I--UN---T-
IO
UTM
A
2
X
1
–
V--V--O--I-U-N--T-
+
1--1--2--
-V---L-I-N-----–---f--VO----SO---C-U---T-
-V--V--O--I--UN---T-
2
(EQ. 10)
For a through-hole design, several electrolytic capacitors may be
needed. For surface mount designs, solid tantalum capacitors
can be used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be capable
of handling the surge current at power-up. Some capacitor series
available from reputable manufacturers are surge current tested.
Feedback Compensation
Figure 36 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage (VOUT)
is regulated to the reference voltage level. The error amplifier
output (VE/A) is compared with the oscillator (OSC) triangular
wave to provide a pulse-width modulated (PWM) wave with an
amplitude of VIN at the PHASE node. The PWM wave is smoothed
by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC gain
and the output filter (LO and CO), with a double pole break
frequency at FLC and a zero at FESR. The DC gain of the
modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage, DVOSC. The ISL8502A
incorporates a feed-forward loop that accounts for changes in the
input voltage. This configuration maintains a constant modulator
gain.
VOSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VOUT
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2
R2
ZFB
VOUT
ZIN
C3 R3
R1
COMP
-
FB
+
R4
ISL8502A
REFERENCE
VOUT
=
0.6
1
+
RR-----14-
FIGURE 36. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
DESIGN AND OUTPUT VOLTAGE SELECTION
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2 x LO x CO
fESR= 2----------x-----E----S--1---R------x-----C-----O---
(EQ. 11)
The compensation network consists of the error amplifier
(internal to the ISL8502A) and the impedance networks, ZIN and
ZFB. The goal of the compensation network is to provide a closed
loop transfer function with the highest 0dB crossing frequency
FN7940 Rev 0.00
October 21, 2011
Page 16 of 20
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