CY7C1440AV33-167BZXC(2005) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1440AV33-167BZXC
(Rev.:2005)
(Rev.:2005)
Cypress Semiconductor
CY7C1440AV33-167BZXC Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Truth Table (continued)[3, 4, 5, 6, 7, 8]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
READ Cycle, Continue Burst
Next
X X XL H
H
L
H
L L-H Q
READ Cycle, Continue Burst
Next
X X XL H
H
L
H H L-H Tri-State
READ Cycle, Continue Burst
Next
H X XL X
H
L
H
L L-H Q
READ Cycle, Continue Burst
Next
H X XL X
H
L
H H L-H Tri-State
WRITE Cycle, Continue Burst
Next
X X XL H
H
L
L
X L-H D
WRITE Cycle, Continue Burst
Next
H X XL X
H
L
L
X L-H D
READ Cycle, Suspend Burst Current X X X L H
H
H
H
L L-H Q
READ Cycle, Suspend Burst Current X X X L H
H
H
H
H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X
H
H
H
L L-H Q
READ Cycle, Suspend Burst Current H X X L X
H
H
H
H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H
H
H
L
X L-H D
WRITE Cycle, Suspend Burst Current H X X L X
H
H
L
X L-H D
Truth Table for Read/Write[5,9,10]
Function (CY7C1440AV33)
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
GW
BWE
BWD
BWC
BWB
BWA
H
H
X
X
X
X
H
L
H
H
H
H
H
L
H
H
H
L
H
L
H
H
L
H
H
L
H
H
L
L
H
L
H
L
H
H
H
L
H
L
H
L
H
L
H
L
L
H
H
L
H
L
L
L
H
L
L
H
H
H
H
L
L
H
H
L
H
L
L
H
L
H
H
L
L
H
L
L
H
L
L
L
H
H
H
L
L
L
H
L
H
L
L
L
L
H
H
L
L
L
L
L
L
X
X
X
X
X
Truth Table for Read/Write[5, 9, 10]
Read
Function (CY7C1442AV33)
GW
BWE
BWB
BWA
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
L
H
L
H
L
L
H
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes:
9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled
at the same time for any given write.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05383 Rev. *B
Page 10 of 27
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