CY7C1441AV33(2013) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1441AV33 Datasheet PDF : 34 Pages
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CY7C1441AV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB,
Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
Input- Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
CLK
Input- Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
Clock counter when ADV is asserted LOW, during a burst operation.
CE1
Input- Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new
external address is loaded.
CE2
Input- Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device. CE3 is assumed active throughout this document for BGA. CE3
is sampled only when a new external address is loaded.
OE
Input- Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input- Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
ADSC
Input- Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH
Input- Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous
LOW, addresses presented to the device are captured
into the burst counter. When ADSP and ADSC are both
in the address
asserted, only
AreDgSisPteirssr.eAc[o1g:0n] iazreed.also
loaded
BWE
Input- Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ
Input- ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
MODE
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPx is controlled by BW[A:H] correspondingly.
Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull up.
VDD
VDDQ
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power Power Supply for the I/O Circuitry.
Supply
VSS
Ground Ground for the Core of the Device.
Document Number: 38-05357 Rev. *K
Page 6 of 34
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