CY7C1441AV33(2013) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1441AV33 Datasheet PDF : 34 Pages
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CY7C1441AV33
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1441AV33 provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep†mode. Two clock
cycles are required to enter into or exit from this “sleep†mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep†mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep†mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
01
00
11
10
11
00
11
10
01
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
00
01
Second
Address
A1:A0
01
10
Third
Address
A1:A0
10
11
10
11
00
11
00
01
Fourth
Address
A1:A0
11
10
01
00
Fourth
Address
A1:A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDDï€ â€“ 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
100
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Document Number: 38-05357 Rev. *K
Page 8 of 34
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