White Electronic Designs
WMS512K8V-XXX
ADDRESS
DATA I/O
TIMING WAVEFORM - READ CYCLE
tRC
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
ADDRESS
CS#
OE#
DATA I/O
tRC
tAA
tACS
tCLZ
tOE
tOLZ
HIGH IMPEDANCE
tCHZ
tOHZ
DATA VALID
READ CYCLE 2 (WE# = VIH)
October 2004
Rev. 8
WRITE CYCLE - WE# CONTROLLED
ADDRESS
CS#
tAS
WE#
DATA I/O
tWC
tAW
tCW
tAH
tWHZ
tWP
tOW
tDW
tDH
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
tWC
ADDRESS
tAW
tAS
tCW
tAH
CS#
WE#
DATA I/O
tWP
tDW
tDH
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
4
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