Nexperia
74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous reset
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
001aad983
Test data is given in Table 9.
Test circuit definitions:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistance.
S1 = Test selection switch
Fig. 14. Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
tr, tf
74HC163-Q100 VCC
6 ns
74HCT163-Q100 3 V
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 kΩ
1 kΩ
S1 position
tPHL, tPLH
open
open
74HC_HCT163_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 12 October 2018
© Nexperia B.V. 2018. All rights reserved
13 / 19