S-25A020A0A-T8T2UD Ver la hoja de datos (PDF) - Unspecified
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S-25A020A0A-T8T2UD Datasheet PDF : 35 Pages
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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A
Rev.5.2_02
Table 16
Item
Ta = ï€40°C to 105°C
Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit
Min. Max. Min. Max. Min. Max.
SCK clock frequency
CS setup time during CS falling
fSCK
ï¼
3.5
ï¼
5.0
ï¼
6.5 MHz
tCSS.CL
90
ï¼
90
ï¼
65
ï¼
ns
CS setup time during CS rising
tCSS.CH
90
ï¼
90
ï¼
65
ï¼
ns
CS deselect time
tCDS
160
ï¼
140
ï¼
110
ï¼
ns
CS hold time during CS falling
tCSH.CL
90
ï¼
90
ï¼
65
ï¼
ns
CS hold time during CS rising
SCK clock time "H"*1
SCK clock time "L"*1
Rising time of SCK clock*2
Falling time of SCK clock*2
SI data input setup time
SI data input hold time
SCK "L" hold time during HOLD rising
tCSH.CH
90
ï¼
90
ï¼
65
ï¼
ns
tHIGH
125
ï¼
95
ï¼
65
ï¼
ns
tLOW
125
ï¼
95
ï¼
65
ï¼
ns
tRSK
ï¼
1
ï¼
1
ï¼
1
ïs
tFSK
ï¼
1
ï¼
1
ï¼
1
ïs
tDS
20
ï¼
20
ï¼
20
ï¼
ns
tDH
30
ï¼
30
ï¼
30
ï¼
ns
tSKH.HH
70
ï¼
70
ï¼
45
ï¼
ns
SCK "L" hold time during HOLD falling
tSKH.HL
40
ï¼
40
ï¼
30
ï¼
ns
SCK "L" setup time during HOLD falling
tSKS.HL
0
ï¼
0
ï¼
0
ï¼
ns
SCK "L" setup time during HOLD rising
Disable time of SO output*2
tSKS.HH
0
ï¼
0
ï¼
0
tOZ
ï¼
100
ï¼
100
ï¼
Delay time of SO output
tOD
ï¼
120
ï¼
90
ï¼
Hold time of SO output
Rising time of SO output*2
Falling time of SO output*2
tOH
0
ï¼
0
ï¼
0
tRO
ï¼
80
ï¼
70
ï¼
tFO
ï¼
80
ï¼
70
ï¼
Disable time of SO output during HOLD falling*2 tOZ.HL
ï¼
100
ï¼
100
ï¼
Delay time of SO output during HOLD rising*2
tOD.HH
ï¼
80
ï¼
80
ï¼
ï¼
ns
75
ns
60
ns
ï¼
ns
50
ns
50
ns
75
ns
60
ns
WP setup time
tWS1
0
ï¼
0
ï¼
0
ï¼
ns
WP hold time
tWH1
0
ï¼
0
ï¼
0
ï¼
ns
WP release / setup time
tWS2
0
ï¼
0
ï¼
0
ï¼
ns
WP release / hold time
tWH2
150
ï¼
150
ï¼
100
ï¼
ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK ïs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.)  tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
8
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