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L9823(2003) データシートの表示(PDF) - STMicroelectronics

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L9823 Datasheet PDF : 12 Pages
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L9823
Output Stages Control
Each output is controlled with its latch and with a common Reset line, which enables all outputs.
The control data are transmitted via the SI input, the timing of the serial interface is shown in Fig. 1.
The device is selected with low CSB signal and the input data are transferred into the 8 bit shift register at every
falling SCLK edge. The rising edge of the CSB latches the new data from the shift register to the drivers.
Figure 1. Timing of the Serial Interface
CSB
tsclch thclcl
tclh
tcll
SCLK
tcsdv
tpcld
SO
not defined
D7
tscld
thcld
SI
D7
D6
tsclcl
thclch
tpchdz
D0
D0
The SPI register data are transferred to the output latch at rising CSB edge. The digital filter between CSB and
the output latch ensures that the data are transferred only after 8 SCLK cycles or multiple of 8 SCLK cycles
since the last CSB falling edge. The CSB changes only at low SCLK.
Diagnostics
The output voltage at all outputs is compared with the diagnostic threshold, typ 0,55 VDD = VDG.
Diagnostic Table for outputs:
Output
off
off
on
on
Output-voltage
> DG-threshold
< DG-threshold
< DG-threshold
> DG-threshold
Status-bit
high
low
low
high
Output-mode
correct operation
fault condition 2)
correct operation
fault condition 1)
Fault condition 1) "output short circuit to Vbat" : For SFPD = Low the output was switched on and the voltage at
the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the
output has been switched off. The diagnostic bit is high.
: For SFPD = High the output was switched on and the voltage at the output exceeds the diagnostics threshold.
The output operates in current regulation mode or has been switched off due to thermal shutdown. The status
bit is high.
Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the
output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur-
rent source, the load is interrupted. The diagnostic bit is low.
At the falling edge of CSB the output status data are transferred to the shift register. When SCB is low, data bits
contained in the shift register are transferred to SO output at every rising SCLK edge.
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