BLOCK DIAGRAM
ENB
OSCout
14-BIT S/R
14-BIT LATCH
OSCin
14-BIT ÷ R COUNTER
CONTROL LOGIC
fin
7-BIT ÷ A COUNTER
10-BIT ÷ N COUNTER
7-BIT LATCH
10-BIT LATCH
DATA
CLK
1-BIT S/R
7-BIT S/R
10-BIT S/R
* FSO is not and cannot be used as a digital phase detector output.
ANALOG
fR
PHASE
DETECTOR
fV
DIGITAL
FREQUENCY
STEERING
LOCK
DETECTOR
SRout
CHARGE
CH
RR
RO
CR
APDout
VDD′
VSS′
MC
FSO
LD
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 10
V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin
± 10
mA
IDD, ISS Supply Current, VDD or VSS Pins
± 30
mA
PD Power Dissipation, per Package
500
mW
Tstg Storage Temperature
– 65 to + 150
°C
TL
Lead Temperature (8–Second Soldering)
260
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tions of any voltage higher than maximum rated
voltages to this high–impedance circuit. For
proper operation it is recommended that Vin and
Vout be constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
MC145159–1
2
MOTOROLA