PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1. I = input, O = output
Name
BS1
BS2
BS3
SIGNAL
XVSS
XT
XTN
VSS
CLKO
RSTN
AREA
SCK
SDO
SDI
ATTN
VDD
SM8213AM
I/O 1
Description
O
RF control main output signal
O
RF DC-level adjustment signal
O
PLL setup signal
I
NRZ signal input pin
–
Crystal oscillator ground. Capacitor connected between XVSS and VDD
I
Oscillator input pin
O
Oscillator output pin
–
Ground
O
76.8 or 38.4 kHz clock output
I
Hardware clear (reset)
O
Sync code detection output (HIGH for minimum 1 sec. on detection)
I
CPU-to-decoder data transfer sync clock
O
Status and received data output to CPU
I
Data input from CPU (including ID data)
O
Interrupt detect signal output pin (Ready for data transmission when LOW)
–
Supply voltage
SM8213AM Paging Receiver Block Diagram
RF
Waveform
Recovery
PLL Circuit
Supply Unit
D/D Converter
POCSAG
Decoder
SM8213
Alert
Melody
IC
SP
CPU Unit
ID
ROM
LCD Driver LCD
NIPPON PRECISION CIRCUITS—3