MC14536B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbol
VDD
Min Typ (Note 6) Max Unit
Output Rise and Fall Time (Pin 13)
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
−
100
200
10
−
50
100
15
−
40
80
Propagation Delay Time
Clock to Q1, 8−Bypass (Pin 6) High
tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 617 ns
tPLH, tPHL = (0.5 ns/pF) CL + 425 ns
tPLH,
ns
tPHL
5.0
−
1800
3600
10
−
650
1300
15
−
450
1000
Clock to Q1, 8−Bypass (Pin 6) Low
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns
tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns
tPLH,
tPHL
5.0
−
10
−
15
−
ms
3.8
7.6
1.5
3.0
1.1
2.3
Clock to Q16
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns
tPLH,
tPHL
5.0
−
10
−
15
−
ms
7.0
14
3.0
6.0
2.2
4.5
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1415 ns
tPHL = (0.66 ns/pF) CL + 567 ns
tPHL = (0.5 ns/pF) CL + 425 ns
tPHL
ns
5.0
−
1500
3000
10
−
600
1200
15
−
450
900
Clock Pulse Width
tWH
5.0
600
300
10
200
100
15
170
85
−
ns
−
−
Clock Pulse Frequency (50% Duty Cycle)
fcl
5.0
−
1.2
0.4 MHz
10
−
3.0
1.5
15
−
5.0
2.0
Clock Rise and Fall Time
tTLH,
5.0
tTHL
10
15
−
No Limit
Reset Pulse Width
tWH
5.0
1000
500
10
400
200
15
300
150
−
ns
−
−
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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