DNC3X3425 データシートの表示（PDF） - Agere -> LSI Corporation

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DNC3X3425

Quad 10/100 Mbits/s Ethernet Transceiver Macrocell

Agere -> LSI Corporation 

Advance Data Sheet

March 2000

DNC3X3425

Quad 10/100 Mbits/s Ethernet Transceiver Macrocell

Table of Contents (continued)

Tables (continued)

Page

Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions.............................................28

Table 28. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions...............................................29

Table 29. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions .......................................................30

Figures

Page

Figure 1. DNC3X3425 Functional Block Diagram ....................................................................................................4

Figure 2. I/Os of the DNC3X3425 Macrocell ............................................................................................................5

Figure 3. DNC MII TX Logic ...................................................................................................................................15

Figure 4. DNC MII RX Logic ...................................................................................................................................15

Figure 5. DNC Maintenance Logic .........................................................................................................................15

Figure 6. Typical Application (One Channel Shown) ..............................................................................................16

Figure 7. Pinout Assignment ..................................................................................................................................17

Figure 8. Typical Single-Channel Twisted-Pair (TP) Interface.................................................................................18

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