NT5SV16M8CT-7K データシートの表示（PDF） - Nanya Technology
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NT5SV16M8CT-7K Datasheet PDF : 66 Pages
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NT5SV32M4CT
NT5SV16M8CT
NT5SV8M16CT
128Mb Synchronous DRAM
Burst Read with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
NOP
NOP
NOP
tRP‡
*
DOUT A 0
DOUT A1
tRP‡
DOUT A0
DOUT A 1
NOP
*
NOP
NOP
NOP
Begin Auto-precharge
Burst Read with Auto-Precharge
* Bank can be reactivated at completion of t R P.
‡ tR P is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
NOP
DOUT A 0
NOP
DOUT A1
DOUT A0
NOP
NOP
NOP
tRP‡
*
DOUT A 2
DOUT A 3
tRP‡
DOUT A 1
DOUT A2
DOUT A3
NOP
*
NOP
Begin Auto-precharge
*Bank can be reactivated at completion of tRP.
‡ tR P is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*
REV 1.0
May, 2001
18
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