ST72652C4T1 データシートの表示（PDF） - STMicroelectronics
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ST72652C4T1
STMicroelectronics
ST72652C4T1 Datasheet PDF : 166 Pages
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ST7265x
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.2 I2C - Inter IC Control Interface
Refer to I/O port characteristics for more details on
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I2C interface meets the
requirements of the Standard I2C communication
protocol described in the following table.
Symbol
Parameter
Standard mode I2C
Min 1)
Max 1)
Fast mode I2C
Min 1)
Max 1)
Unit
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
th(SDA) SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
tf(SDA)
tf(SCL)
SDA and SCL fall time
th(STA) START condition hold time
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
tw(STO:STA) STOP to START condition time (bus free)
Cb
Capacitive load for each bus line
4.7
1.3
µs
4.0
0.6
250
100
0 3)
0 2)
900 3)
1000 20+0.1Cb 300
ns
300 20+0.1Cb 300
4.0
0.6
µs
4.7
0.6
4.0
0.6
ns
4.7
1.3
ms
400
400
pF
Figure 102. Typical Application with I2C Bus and Timing Diagram 4)
VDD
VDD
I2C BUS
4.7kΩ
SDA
START
4.7kΩ
100Ω
100Ω
SDAI
SCLI
ST72XXX
REPEATED START
tsu(STA)
tw(STO:STA) START
tf(SDA)
tr(SDA)
tsu(SDA) th(SDA)
STOP
SCK
th(STA) tw(SCKH) tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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