VPX3224E データシートの表示（PDF） - Micronas

部品番号

コンポーネント説明

メーカー

VPX3224E

Video Pixel Decoders

Micronas 

ADVANCE INFORMATION

1.1. System Architecture

The block diagram (Fig. 1–1) illustrates the signal flow

through the VPX. A sampling stage performs 8-bit A/D

conversion, clamping, and AGC. The color decoder sep-

arates the luma and chroma signals, demodulates the

chroma, and filters the luminance. A sync slicer detects

the sync edge and computes the skew relative to the

sample clock. The video processing stage resizes the

YCbCr samples, adjusts the contrast and brightness,

and interpolates the chroma. The text slicer extracts

lines with text information and delivers decoded data

bytes to the video interface.

Note: The VPX 322xE is register compatible with the

VPX 322xD family, but not with VPX 3220A, VPX 3216B,

and VPX 3214C family.

VPX 322xE

Clock Gen.

DCO

CVBS/Y

ADC

Chroma

SDA

SCL

ADC

I2C

JTAG

Sync Processing

Text Slicer

(not VPX 3224E)

Y

Luma Filter

Video Decoder

Chroma

Demodulator

CbCr

Y

CbCr

Line Store

Fig. 1–1: Block diagram of the VPX 322xE

Micronas

HREF

VREF

FIELD

A[7:0]

OEQ

B[7:0]

PIXCLK

LLC

VACT

7

Share Link: