AD9705 データシートの表示（PDF） - Analog Devices
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AD9705 Datasheet PDF : 52 Pages
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AD9704/AD9705/AD9706/AD9707
Parameter
Supply Current Clock Power-
Down Mode (IDVDD)5
Supply Current Clock Power-
Down Mode (ICLKVDD)
Power Supply Rejection Ratio
(AVDD) 6
OPERATING RANGE
AD9707
AD9706
AD9705
AD9704
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
0.6 1
0.6 1
0.6 1
0.6 1
mA
42.5 58
42.5 58
42.5 58
42.5 58
μA
−0.2 +0.03 +0.2 −0.2 +0.03 +0.2 −0.2 +0.03 +0.2 −0.2 +0.03 +0.2 % of FSR/V
−40
+85 −40
+85 −40
+85 −40
+85 °C
1 Measured at IOUTA, driving a virtual ground, at 25°C only.
2 Nominal full-scale current, IOUTFS, is 32× the IREF current.
3 An external buffer amplifier with input bias current < 100 nA should be used to drive any external load.
4 Measured at fCLOCK = 175 MSPS and fOUT = 1.0 MHz, using differential clock.
5 Measured at fCLOCK = 100 MSPS and fOUT = 1.0 MHz, using differential clock.
6 ±5% power supply variation.
DYNAMIC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, differential transformer coupled output,
453 Ω differentially terminated,1 unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)2
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)2
Output Fall Time (10% to 90%)2
AC LINEARITY
Spurious-Free Dynamic Range
to Nyquist
fCLOCK = 10 MSPS; fOUT = 2.1 MHz
fCLOCK = 25 MSPS; fOUT = 2.1 MHz
fCLOCK = 65 MSPS; fOUT = 5.1 MHz
fCLOCK = 65 MSPS; fOUT = 10.1 MHz
fCLOCK = 80 MSPS; fOUT = 1.0 MHz
fCLOCK = 125 MSPS; fOUT = 15.1 MHz
fCLOCK = 125 MSPS; fOUT = 25.1 MHz
fCLOCK = 175 MSPS; fOUT = 20.1 MHz
fCLOCK = 175 MSPS; fOUT = 40.1 MHz
Noise Spectral Density
fCLOCK = 175 MSPS; fOUT = 6.0 MHz;
IOUTFS = 2 mA
ENOB at IOUTFS = 2 mA
fCLOCK = 175 MSPS; fOUT = 6.0 MHz;
IOUTFS = 5 mA
ENOB at IOUTFS = 5 mA
fCLOCK = 175 MSPS; fOUT = 6.0 MHz;
IOUTFS = 1 mA
ENOB at IOUTFS = 1 mA
AD9707
AD9706
AD9705
AD9704
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
175
11
4
5
2.5
2.5
175
11
4
5
2.5
2.5
175
11
4
5
2.5
2.5
175
11
4
5
2.5
2.5
84
84
84
83
74 83
78
77
75
72
−149
11.3
−157
12.5
−145
10.6
84
83
84
83
72 82
78
77
75
71
−146
10.9
84
84
84
83
72 82
78
76
75
71
−137
9.5
70
68
70
71
66 70
68
69
69
67
−127
8.0
Unit
MSPS
ns
ns
pV-s
ns
ns
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/
Hz
bits
dBc/
Hz
bits
dBc/
Hz
bits
1 See Figure 71 for diagram.
2 Measured single-ended into 500 Ω load.
Rev. 0 | Page 5 of 52
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