MT6225ACS データシートの表示（PDF） - Unspecified

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MT6225ACS

GSM/GPRS Baseband Processor

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MT6225 GSM/GPRS Baseband Processor Data Sheet Revision 1.00

3 Micro-Controller Unit Subsystem

Figure 6 illustrates the block diagram of the Micro-Controller Unit Subsystem in MT6225. The subsystem utilizes a

main 32-bit ARM7EJ-S RISC processor, which plays the role of the main bus master controlling the whole subsystem.

All processor transactions go to code cache first. The code cache controller accesses TCM (72KB memory dedicated

to ARM7EJS core), cache memory, or bus according to the processor’s request address. If the requested content is

found in TCM or in cache, no bus transaction is required. If the code cache hit rate is high enough, bus traffic can be

effectively reduced and processor core performance maximized. In addition to the benefits of reuse of memory

contents, code cache also has a MPU (Memory Protection Unit), which allows cacheable and protection settings of

predefined regions. The contents of code cache are only accessible to MCU, and only MCU instructions are kept in

the cache memory (thus the name “code” cache).

The bus comprises of two-level system buses: Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus

(APB). All bus transactions originate from bus masters, while slaves can only respond to requests from bus masters.

Before data transfer can be established, the bus master must ask for bus ownership, accomplished by request-grant

handshaking protocol between masters and arbiters.

Two levels of bus hierarchy are designed to provide optimum usage for different performance requirements.

Specifically, AHB Bus, the main system bus, is tailored toward high-speed requirements and provides 32-bit data path

with multiplex scheme for bus interconnections. The APB Bus, on the other hand, is designed to reduce interface

complexity for lower data transfer rate, and so it is isolated from high bandwidth AHB Bus by APB Bridge. APB Bus

supports 16-bit addressing and both 16-bit and 32-bit data paths. APB Bus is also optimized for minimal power

consumption by turning off the clock when there is no APB bus activity.

During operation, if the target slave is located on AHB Bus, the transaction is conducted directly on AHB Bus.

However, if the target slave is a peripheral and is attached to the APB bus, then the transaction is conducted between

AHB and APB bus through the use of APB Bridge.

The MT6225 MCU subsystem supports only memory addressing method. Therefore all components are mapped onto

the MCU 32-bit address space. A Memory Management Unit is employed to allow for a central decode scheme.

The MMU generates appropriate selection signals for each memory-addressed module on the AHB Bus.

In order to off-load the processor core, a DMA Controller is designated to act as a master and share the bus resources

on AHB Bus to do fast data movement between modules. This controller comprises thirteen DMA channels.

The Interrupt Controller provides a software interface to manipulate interrupt events. It can handle up to 32 interrupt

sources asserted at the same time. In general, it generates 2 levels of interrupt requests, FIQ and IRQ, to the processor.

A 128K Byte SRAM is provided for acting as system memory for high-speed data access. For factory programming

purpose, a Boot ROM module is used. These two modules use the same Internal Memory Controller to connect to AHB

Bus.

External Memory Interface supports both 8-bit and 16-bit devices. Since AHB Bus is 32-bit wide, all the data transfer

will be converted into several 8-bit or 16-bit cycles depending on the data width of target device. Note that, this

interface is specific to both synchronous and asynchronous components, like Flash, SRAM and parallel LCD. This

interface supports also page and burst mode type of Flash.

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