GT-6816 データシートの表示（PDF） - Unspecified

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GT-6816

SCANNER Chips

Unspecified 

GT-6816

5:0 6’b0 Define falling phase referenced to 6-bits pixel clock counter

Sensor H2 control signal rising phase

CPU Read/Write

Address: FF1CH

Bit Reset Description

7 1’b0 H2 polarity

0 = normal operation.

1 = invert H2 output

6 1’b0 H2 enable

0 = disable H2 output

1 = enable H2 output

5:0 6’b0 Define rising phase referenced to 6-bits pixel clock counter

Sensor H2 control signal falling phase

CPU Read/Write

Address: FF1DH

Bit Reset Description

7 1’b0 H2 half enable

6 1’b0 H2 masking function enable

0 = disable masking function

1 = enable masking function

5:0 6’b0 Define falling phase referenced to 6-bits pixel clock counter

AFE CLAMP0 control signal rising phase

CPU Read/Write

Address: FF1EH

Bit Reset Description

7:0 8’b0 Define rising phase referenced to 16-bits counter

AFE CLAMP0 control signal falling phase

CPU Read/Write

Address: FF1FH

Bit Reset Description

7:0 8’b0 Define falling phase referenced to 16-bits counter

Note:

These two registers define the rising and falling phase of CLAMP0 control signal, and

only available on the first 256 cycles of 16-bits counter. CLAMP0 output ‘0’ when

16-bits counter exceeds 256 cycle.

AFE CCLP0 control signal rising phase

CPU Read/Write

Address: FF20H

18

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