INIC-1511 データシートの表示（PDF） - Unspecified

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コンポーネント説明

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INIC-1511

USB to PATA Bridge

Unspecified 

INIC-1511 (Preliminary)

6.2.21 I2C_Addr Register (0x0E0)

Field name

rscu bit reset

#

I2C_Addr

rw 7-0 8’h0

Description

CPU writes the to-be executed NVRAM address to this

register.

6.2.22 I2C_Data Register (0x0E1) (I2C Data port)

Field name

rscu bit reset Description

#

I2C_Data

rw 7-0 8’h0 This is the data port for CPU to access NVRAM

A: To Write to NVRAM:

CPU Writes a 8-bit data to this port, Hardware will send

this data to NVRAM

B: To Read from NVRAM:

CPU reads this port to get data from NVRAM

6.2.23 I2C_Ctrl Register (0x0E2) (I2C Control Code)

Field name

rscu bit reset Description

#

Reserved

w 7 1’b0 reserved

Control_Code

rw 6:3 4’b0 Control Code

Block_Select

rw 2:0 3’b0 I2C device block select bits

6.2.24 I2C_COMM Register (0x0E3)

Field name

rscu bit reset

#

I2C_TX_START rw 7 1’b0

reserved

Rd_nWr

rw 6:1 6’b0

wr 0 1’b0

Description

1-> Hardware start to Read/Write NVRAM. Clear by

hardware when finished.

reserved

0-> write to NVRAM

1-> read data from NVRAM

6.2.25 I2C_Status Register (0x0E4)

Field name

rscu bit reset

#

reserved

rw 7-3 5’b0

Data_Ack

r 0 1’b0

Addr_Ack

r 0 1’b0

Ctrl_Ack

r 0 1’b0

Description

reserved

0-> NVRAM ACK with Data write phase

1->NVRAM NACK with Data write phase

0-> NVRAM ACK with Address write phase

1->NVRAM NACK with Address write phase

0-> NVRAM ACK with Contrl Code write phase

1->NVRAM NACK with Contrl Code write phase

Initio Corporation Confidential

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