EP1C12T173C6 データシートの表示（PDF） - Altera Corporation

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EP1C12T173C6

Cyclone FPGA Family

Altera Corporation 

Logic Elements

Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full

adder. One portion of the LUT generates the sum of two bits using the

input signals and the appropriate carry-in bit; the sum is routed to the

output of the LE. The register can be bypassed for simple adders or used

for accumulator functions. Another portion of the LUT generates carry-

out bits. An LAB-wide carry-in bit selects which chain is used for the

addition of given inputs. The carry-in signal for each chain, carry-in0

or carry-in1, selects the carry-out to carry forward to the carry-in

signal of the next-higher-order bit. The final carry-out signal is routed to

an LE, where it is fed to local, row, or column interconnects.

Figure 2–8. Carry Select Chain

LAB Carry-In

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

01

LE1

Sum1

LE2

Sum2

LE3

Sum3

LE4

Sum4

LE5

Sum5

01

A6

LE6

Sum6

B6

A7

LE7

Sum7

B7

A8

LE8

Sum8

B8

A9

LE9

Sum9

B9

A10

LE10 Sum10

B10

LAB Carry-In

Carry-In0

Carry-In1

data1

data2

LUT

Sum

LUT

LUT

LUT

Carry-Out0 Carry-Out1

LAB Carry-Out

Altera Corporation

January 2007

2–11

Preliminary

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