WM8501(2006) データシートの表示（PDF） - Wolfson Microelectronics plc

部品番号

コンポーネント説明

メーカー

WM8501
(Rev.:2006)

24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver

Wolfson Microelectronics plc 

Pre-Production

WM8501

HARDWARE CONTROL MODES

The WM8501 is hardware programmable providing the user with options to select input audio data

format, de-emphasis and mute.

ENABLE OPERATION

Pin 4 (ENABLE) controls the operation of the chip. If ENABLE is low the device is held in a low

power state. If this pin is held high the device is powered up.

To ensure correct operation it is essential that there is a low to high transition on the ENABLE pin

after digital supplies have come on. This can be achieved by providing the ENABLE signal from

an external controller chip or by means of a simple RC network on the ENABLE pin. See

“Recommended External Components” in the “Application Information” section at the end of this

datasheet.

Note that the ENABLE pin should not be used as a mute pin or to temporarily silence the DAC

(between tracks of a CD for example). The ENABLE pin is not intended to be used as a mute

control but to allow entry into low power mode. Disabling the device via the ENABLE pin has the

effect of powering down the voltage on the VMID pin. Repeated enabling/disabling of the device

can cause audible pops at the output.

HIGH PERFORMANCE MODE

On the rising edge of ENABLE, the DEEMPH pin is sampled. If it is low the device powers up

normally. If it is high the device goes into a high performance and high power consumption state.

Once ENABLE is high, DEEMPH controls the selection of the de-emphasis filter.

INPUT AUDIO FORMAT SELECTION

FORMAT (pin 13) controls the data input format.

FORMAT

INPUT DATA MODE

0

16 bit right justified

1

16–24 bit I2S

Table 2 Input Audio Format Selection

Notes:

1. In 16-24 bit I2S mode, any data from 16-24 bits or more is supported provided that LRCLK is

high for a minimum of data width BCLKs and low for a minimum of data width BCLKs,

unless Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the

most significant 24 bits will be used by the internal processing.

2. If exactly 16 BCLK cycles occur in both the low and high period of LRCLK the WM8501 will

assume the data is 16-bit and accept the data accordingly.

INPUT DSP FORMAT SELECTION

FORMAT

0

1

50% LRCLK DUTY CYCLE

16 bit

(MSB-first, right justified)

I2S format up to 24 bit

(Philips serial data protocol)

Table 3 DSP Interface Formats

LRCLK of 4 BCLK or Less Duration

DSP format –mode B

DSP format –mode A

DE-EMPHASIS CONTROL

DEEMPH (pin 12) is an input control for selection of de-emphasis filtering to be applied.

DEEMPH

0

1

Table 4 De-emphasis Control

DE-EMPHASIS

Off

On

w

PP Rev 3.1 May 2006

13

Share Link: