AGL030V2-VQG144YES データシートの表示（PDF） - Microsemi Corporation

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AGL030V2-VQG144YES

IGLOO Low Power Flash FPGAs with Flash* Freeze Technology

Microsemi Corporation 

IGLOO Low Power Flash FPGAs

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

• Maximum acquisition time is 300 µs (for PLL only)

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC (for PLL only)

Global Clocking

IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL

support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V,

1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-

ended and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these banks

determines the I/O standards supported (Table 1-1).

Table 1-1 • I/O Standards Supported

I/O Standards Supported

I/O Bank Type

Device and Bank Location

LVTTL/ PCI/PCI-X LVPECL, LVDS,

LVCMOS

B-LVDS, M-LVDS

Advanced

East and west banks of AGL250 and larger 





devices

Standard Plus North and south banks of AGL250 and 

larger devices

All banks of AGL060 and AGL125K



Not supported

Standard

All banks of AGL015 and AGL030

 Not supported Not supported

Revision 23

1-7

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