INTERNAL REGISTER MAP
ADDRESS
REGISTER DEFINITION
ACCESS
0
CONTROL
1
POINTER TABLE ADDRESS
R/W
R/W
2
BASIC STATUS
3
INTERRUPT MASK(lower byte)
R/W
R/W
3
INTERRUPT VECTOR(upper byte)
R
3
INTERRUPT REQUEST(upper byte)
W
4
INTERRUPT VECTOR(lower byte)
4
AUXILLARY VECTOR(upper byte)
R/W
R
4
RESERVED(upper byte)
W
5
REAL TIME CLOCK HIGH WORD
R
6
REAL TIME CLOCK LOW WORD
R
7
REAL TIME CLOCK CONTROL
8
READ FIFO
R/W
R
8
RESET FIFO
W
9
CONFIGURATION 1
R/W
10
RESERVED
11
LAST COMMAND
R
12
LAST STATUS
R
13
RESERVED
14
RESERVED
15
RESET TERMINAL(both bytes)
W
16
RESERVED
17
RESERVED
18
ENCODER STATUS
R
19
CONDITION
R
20
RESERVED
21
CONFIGURATION 3
R/W
22
RESERVED
23
ENCODER DATA*
24
ENCODER DATA TX REQUEST*
R/W
W
25
ENCODER COMMAND TX REQUEST*
W
26
RESERVED
27
RESERVED
28
RESERVED
29
RESERVED
30
EXTERNAL RTU ADDRESS BUFFER(lowre byte)
R
30
COMMAND OUTPUT PINS
W
31
I/O TAG WORD
R/W
DO NOT WRITE TO RESERVED REGISTERS.
*In order to write to addresses 23, 24, or 25, the RT must be in loop- back mode (see CONTROL
register for details).
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