AM29F400AT-90EC データシートの表示（PDF） - Advanced Micro Devices
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AM29F400AT-90EC
Advanced Micro Devices
AM29F400AT-90EC Datasheet PDF : 35 Pages
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PRELIMINARY
Table 7. Am29F400A Command Definitions (Notes 1–7)
Command
Sequence
Read/Reset
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Addr Data
Second Bus
Write Cycle
Addr Data
Third Bus
Write Cycle
Addr Data
Fourth Bus
Read/Write Cycle
Addr
Data
Fifth Bus Sixth Bus
Write Cycle Write Cycle
Addr Data Addr Data
Reset/Read
1 XXXXH F0H
Reset/
Read
Word
5555H AAH 2AAAH 55H 5555H
3
F0H RA
Byte
AAAAH
5555H
AAAAH
RD
Word 3 5555H AAH 2AAAH 55H 5555H 90H 01H 2223H
(T Device ID)
22ABH
(B Device ID)
Autoselect Byte
AAAAH
5555H
AAAAH
23H
(T Device ID)
ABH
(B Device ID)
Word
/Byte
00H
01H (T/B
Manuf. ID)
Word 4 5555H AAH 2AAAH 55H 5555H A0H PA
PD
Program
Byte
AAAAH
5555H
AAAAH
Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H
Chip Erase
Byte
AAAAH
5555H
AAAAH
AAAAH
AAH
2AAAH 55H 5555H 10H
5555H
AAAAH
Sector
Erase
Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H
Byte
AAAAH
5555H
AAAAH
AAAAH
AAH
2AAAH 55H SA 30H
5555H
Erase Suspend
1 XXXXH B0H
Erase Resume
1 XXXXH 30H
Notes:
1. Bus operations are defined in Tables 1 and 2.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A17–A12 will uniquely select any sector.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
4. Reading from non-erasing sectors is allowed in the Erase Suspend mode.
5. Address bits A17–A15 are don’t care for unlock and command cycles.
6. The system should generate the following address patterns:
Word Mode: 5555H or 2AAAH to addresses A0–A14
Byte Mode: AAAAH or 5555H to addresses A-1–A14.
Read/Reset Command
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
12
Am29F400AT/Am29F400AB
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