IS61LV6464 データシートの表示（PDF） - Integrated Circuit Solution Inc

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IS61LV6464

64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

Integrated Circuit Solution Inc 

IS61LV6464

WRITE CYCLE TIMING

CLK

ADSP

ADSC

ADV

A15-A0

GW

BWE

BW8-BW1

CE

CE2, CE3

CE2, CE3

tKC

tKH

tKL

tSS

tSH

ADV must be inactive for ADSP Write tAVS

tAS

tAH

WR1

tWS

WR2

tWH

ADSP is blocked by CE inactive

ADSC initiate Write

tAVH

WR3

tWS

tWH

tWS

tWH

tWS

tWH

WR1

WR2

WR3

tCES

tCEH

CE Masks ADSP

tCES

tCEH

CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC

tCES

tCEH

Unselected with CE2, CE3

OE

DATAOUT

High-Z

tDS

tDH BW8-BW1 only are applied to first cycle of WR2

DATAIN

High-Z

1a

2a

2b

2c

2d

3a

Single Write

Burst Write

Write

Unselected

12

Integrated Circuit Solution Inc.

SSR010-0B

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