MAX1065(2002) データシートの表示（PDF） - Maxim Integrated

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MAX1065
(Rev.:2002)

Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface

Maxim Integrated 

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Detailed Description

Converter Operation

The MAX1065/MAX1066 use a successive-approximation

(SAR) conversion technique with an inherent track-and-

hold (T/H) stage to convert an analog input into a 14-bit

digital output. Parallel outputs provide a high-speed inter-

face to most microprocessors (µPs). The Functional

Diagram shows a simplified internal architecture of the

MAX1065/MAX1066. Figure 3 shows a typical application

circuit for the MAX1066.

DVDD

D0–D13

1mA

D0–D13

1mA

CLOAD = 20pF

CLOAD = 20pF

DGND

DGND

a) HIGH-Z TO VOH,

VOL TO VOH, AND

VOH TO HIGH-Z

b) HIGH-Z TO VOL,

VOH TO VOL, AND

VOL TO HIGH-Z

Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13

Delay Time and Bus Relinquish Time

Analog Input

The equivalent input circuit is shown in Figure 4. A

switched capacitor digital-to-analog converter (DAC)

provides an inherent track-and-hold function. The sin-

gle-ended input is connected between AIN and AGND.

Input Bandwidth

The ADC’s input-tracking circuitry has a 4MHz small-

signal bandwidth, so it is possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid aliasing of

unwanted high-frequency signals into the frequency

band of interest, use antialias filtering.

Internal protection diodes, which clamp the analog

input to AVDD and/or AGND, allow the input to swing

from AGND - 0.3V to AVDD + 0.3V, without damaging

the device.

If the analog input exceeds 300mV beyond the sup-

plies, limit the input current to 10mA.

Track and Hold (T/H)

In track mode, the analog signal is acquired on the

internal hold capacitor. In hold mode, the T/H switches

open and the capacitive DAC samples the analog input.

CS

R/C

EOC

D0–D13

tCSL

tCSH

tACQ

REF POWER-

DOWN BIT

tDH

tDS

HI–Z

tCONV

tDV

tDO

tEOC

tBR

HI-Z

DATA VALID

HBEN*

D7/D13–D0/D8*

tDO1

HIGH/LOW

BYTE VALID

tBR

HIGH/LOW

BYTE VALID

*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.

Figure 2. MAX1065/MAX1066 Timing Diagram

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