Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 105.0006MHz, CL ≈ 10pF. TA = +25°C, unless
otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.065
OUTPUT NOISE HISTOGRAM (DC INPUT)
7000
64676
6000
2.055
5000
2.045
4000
2.035
2.025
2.015
-40 -15
10
35
60
85
TEMPERATURE (°C)
3000
2000
1000
0
607
0
252
0
N-2 N-1 N N+1 N+2
DIGITAL OUTPUT NOISE
PIN
1
2, 6, 11, 14, 15
3, 7, 10, 13, 16
4
5
8
9
12
17
18
19
20
NAME
COM
VDD
GND
INA+
INA-
INB-
INB+
CLK
T/B
SLEEP
PD
OE
Pin Description
FUNCTION
Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.
Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. The analog
supply accepts a 2.7V to 3.6V input range.
Analog Ground
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
Converter Clock Input
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
Power-Down Input.
High: Power-down mode
Low: Normal operation
Output Enable Input.
High: Digital outputs disabled
Low: Digital outputs enabled
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