MAX1213(2004) データシートの表示（PDF） - Maxim Integrated

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MAX1213
(Rev.:2004)

1.8V, 12-Bit, 170Msps ADC for Broadband Applications

Maxim Integrated 

1.8V, 12-Bit, 170Msps ADC for

Broadband Applications

ELECTRICAL CHARACTERISTICS (continued)

(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,

internal reference, digital output pins differential RL = 100Ω ±1%, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by

production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

LVCMOS DIGITAL INPUTS (CLKDIV, T/B)

CONDITIONS

MIN TYP MAX UNITS

Digital Input Voltage Low

VIL

Digital Input Voltage High

VIH

TIMING CHARACTERISTICS

0.2 x AVCC V

0.8 x AVCC

V

CLK-to-Data Propagation Delay

CLK-to-DCLK Propagation Delay

DCLK-to-Data Propagation Delay

LVDS Output Rise Time

LVDS Output Fall Time

tPDL

Figure 4

tCPDL Figure 4

tPDL - tCPDL Figure 4 (Note 2)

tRISE

20% to 80%, CL = 5pF

tFALL 20% to 80%, CL = 5pF

1.85

ns

4.815

ns

2.5 2.965 3.4

ns

460

ps

460

ps

Output Data Pipeline Delay

tLATENCY Figure 4

11

Clock

cycles

POWER REQUIREMENTS

Analog Supply Voltage Range

Digital Supply Voltage Range

Analog Supply Current

Digital Supply Current

Analog Power Dissipation

Power-Supply Rejection Ratio

(Note 3)

AVCC

OVCC

IAVCC

IOVCC

PDISS

PSRR

fIN = 65MHz

fIN = 65MHz

fIN = 65MHz

Offset

Gain

1.70 1.80 1.90

V

1.70 1.80 1.90

V

483

555

mA

58

67

mA

975 1120 mW

1.8

mV/V

1.5

%FS/V

Note 1: Static linearity and offset parameters are based on the end-point fit method. The full-scale range (FSR) is defined as 4095 x

slope of the line.

Note 2: Parameter guaranteed by design and characterization: TA = TMIN to TMAX.

Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.

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