MAX1452
Low-Cost Precision Sensor
Signal Conditioner
Detailed Block Diagram
VDD
ISRC
VDD
FSO
DAC
VSS
RISRC
75kΩ
VSS
RSTC
75kΩ
FSOTC
BDR
INP
16-BIT
FSOTC
DAC
PHASE VSS
REVERSAL
MUX
FSOTC REGISTER
MUX
∑
x 26
16-BIT
±1
EEPROM
(LOOKUP PLUS CONFIGURATION DATA)
EEPROM ADDRESS USAGE
000H + 001H
:
OFFSET DAC LOOKUP TABLE
(176 x 16-BITS)
VDD
OFFSET
DAC
16-BIT
15EH + 15FH
160H + 161H
162H + 163H
164H + 165H
166H + 167H
168H + 169H
16AH + 16BH
16CH + 16DH
:
CONFIGURATION REGISTER SHADOW
RESERVED
OFFSET TC REGISTER SHADOW
RESERVED
FSOTC REGISTER SHADOW
CONTROL LOCATION REGISTER
USER STORAGE (52 BYTES)
VSS
19EH + 19FH
1A0H + 1A1H FSO DAC LOOKUP TABLE
:
(176 x 16-BITS)
VDD
2FEH + 2FFH
BANDGAP
TEMP
SENSOR
∑∆
8-BIT
LOOKUP
ADDRESS
DIGITAL
INTERFACE
VSS
PGA BANDWIDTH
3kHz 10%
PGA
∑
MUX
INM
VSS
INPUT REFERRED OFFSET
(COARSE OFFSET)
IRO (3, 2:0) OFFSET mV
±1
1,111
63
1,110
54
1,101
45
1,100
36
1,011
27
1,010
18
16-BIT
OFFSET
TC DAC
1,001
1,000
9
OTC REGISTER
VSS
0
0,000
0,001
0,010
0,011
0,100
0,101
0
-9
* INPUT REFERRED
-18
OFFSET VALUE IS
-27
PROPORTIONAL TO VDD.
VALUES GIVEN ARE FOR
-36
VDD = 5V.
-45
0,110
-54
0,111
-63
PROGRAMMABLE GAIN STAGE
PGA (3:0) PGA GAIN TOTAL GAIN
0000
1.5
39
0001
2.0
52
0010
2.5
65
0011
3.0
78
0100
3.5
91
0101
4.0
104
0110
4.5
117
0111
5.0
130
1000
5.5
143
1001
6.0
156
1010
6.5
169
1011
7.0
182
1100
7.5
195
1101
8.0
208
1110
8.5
221
1111
9.0
234
PGA BANDWIDTH 3kHz ± 10%
UNCOMMITTED OP AMP
PARAMETER
I/P RANGE
I/P OFFSET
O/P RANGE
NO LOAD
1mA LOAD
UNITY GBW
VALUE
VSS TO VDD
±20mV
VSS, VDD ±0.01V
VSS, VDD ±0.25V
10MHz TYPICAL
VDD
VSS
TEST
CLK1M
VDDF
UNLOCK
DIO
OUT
AMP-
AMPOUT
AMP+
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