MAX8760 データシートの表示（PDF） - Maxim Integrated

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MAX8760

Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies

Maxim Integrated 

Dual-Phase, Quick-PWM Controller for AMD

Mobile Turion 64 CPU Core Power Supplies

Table 3. Operating Mode Truth Table

SHDN

SUS

SKIP

OFS

OUTPUT

VOLTAGE

GND

x

x

x

GND

VCC

GND

VCC

GND or REF

D0–D5

(no offset)

VCC

x

GND

or

GND or REF

D0–D5

(no offset)

REF

OPERATING MODE

Low-Power Shutdown Mode. DL_ is forced high, DH_ is

forced low, and the PWM controller is disabled. The supply

current drops to 1µA (typ).

Normal Operation. The no-load output voltage is determined by

the selected VID DAC code (D0–D5, Table 4).

Pulse-Skipping Operation. When SKIP is pulled low, the

MAX8760 immediately enters pulse-skipping operation

allowing automatic PWM/PFM switchover under light loads.

The VROK upper threshold is blanked.

VCC

GND

0 to 0.8V

Deep-Sleep Mode. The no-load output voltage is determined

x

or

1.2V to 2V

D0–D5

(plus offset)

by the selected VID DAC code (D0–D5, Table 4) plus the

offset voltage set by OFS.

REF

VCC

or

x

High

x

SUS, S0–S1

(no offset)

Suspend Mode. The no-load output voltage is determined by

the selected suspend code (SUS, S0, S1, Table 5),

overriding all other active modes of operation.

Fault Mode. The fault latch has been set by either UVP, OVP,

VCC

x

x

x

GND

or thermal shutdown. The controller remains in FAULT mode

until VCC power is cycled or SHDN toggled.

Four-Level Logic Inputs

TON and S0, S1 are four-level logic inputs. These inputs

help expand the functionality of the controller without

adding an excessive number of pins. The four-level

inputs are intended to be static inputs. When left open,

an internal resistive voltage-divider sets the input volt-

age to approximately 3.5V. Therefore, connect the four-

level logic inputs directly to VCC, REF, or GND when

selecting one of the other logic levels. See the Electrical

Characteristics table for exact logic level voltages.

Suspend Mode

When the processor enters low-power suspend mode, it

sets the regulator to a lower output voltage to reduce

power consumption. The MAX8760 includes independent

suspend-mode output voltage codes set by the four-level

S0, S1 inputs and the tri-level SUS input. When the CPU

suspends operation (SUS = REF or high), the controller

disables the offset amplifier and overrides the 5-bit VID

DAC code set by either D0–D5 (normal operation). The

master controller slews the output to the selected sus-

pend-mode voltage. During the transition, the MAX8760

blanks VROK and the UVP fault protection until 24 RTIME

clock cycles after the slew-rate controller reaches the

suspend-mode voltage.

SUS is a tri-level logic input: GND, REF, or high. This

expands the functionality of the controller without

adding an additional pin. This input is intended to be

driven by a dedicated open-drain output with the pullup

resistor connected either to REF (or a resistive divider

from VCC) or to a logic-level bias supply (3.3V or

greater). When pulled up to REF, the MAX8760 selects

the upper suspend voltage range. When pulled high

(2.7V or greater), the controller selects the lower sus-

pend voltage range. See the Electrical Characteristics

table for exact logic-level voltages.

Output Voltage Transition Timing

The MAX8760 is designed to perform mode transitions in

a controlled manner, automatically minimizing input surge

currents. This feature allows the circuit designer to

achieve nearly ideal transitions, guaranteeing just-in-time

arrival at the new output voltage level with the lowest pos-

sible peak currents for a given output capacitance.

At the beginning of an output voltage transition, the

MAX8760 blanks the VROK output, preventing it from

changing states. VROK remains blanked during the

transition and is enabled 24 clock cycles after the

slew-rate controller has set the final DAC code value.

The slew-rate clock frequency (set by resistor RTIME)

must be set fast enough to ensure that the transition is

completed within the maximum allotted time.

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