MAX8760 データシートの表示（PDF） - Maxim Integrated
部品番号
コンポーネント説明
メーカー
MAX8760
Maxim Integrated
MAX8760 Datasheet PDF : 39 Pages
| |||
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
D0–D5
D0
DECODER
D1
SUSPEND
D2
MUX
D3
IN
D4
OUT
0
D5
S0, S1
DECODER
S0
IN
S1
OUT
1
OUT
DAC
SEL
SEL
SUS
2.5V
1.0V
SUS 3-LEVEL
DECODER
Figure 3. Internal Multiplexers Functional Diagram
The slew-rate controller transitions the output voltage in
12.5mV steps during soft-start, soft-shutdown, and sus-
pend-mode transitions. The total time for a transition
depends on RTIME, the voltage difference, and the
accuracy of the MAX8760’s slew-rate clock, and is not
dependent on the total output capacitance. The greater
the output capacitance, the higher the surge current
required for the transition. The MAX8760 automatically
controls the current to the minimum level required to
complete the transition in the calculated time, as long
as the surge current is less than the current limit set by
ILIM. The transition time is given by:
tSLEW
≈
1
fSLEW
⎛
⎝⎜
VOLD − VNEW
VLSB
⎞
⎠⎟
for
VOUT
rising
tSLEW
≈
1
fSLEW
⎡⎛
⎣⎢⎢⎝⎜
VOLD − VNEW
VLSB
⎞
⎠⎟
⎤
+ 2⎥
⎦⎥
for
VOUT
falling
where fSLEW = 500kHz ✕ 30kΩ / RTIME, VOLD is the
original DAC setting, VNEW is the new DAC setting, and
VLSB = 12.5mV is the DAC’s smallest voltage incre-
ment. The additional two clock cycles on the falling
edge time are due to internal synchronization delays.
See TIME Frequency Accuracy in the Electrical
Characteristics table for fSLEW limits.
The practical range of RTIME is 15kΩ to 150kΩ, corre-
sponding to 1.0µs to 10µs per 12.5mV step. Although
the DAC takes discrete steps, the output filter makes
the transitions relatively smooth. The average inductor
current required to make an output voltage transition is:
IL ≅ COUT × VLSB × fSLEW
______________________________________________________________________________________ 21
Share Link: 