MAX9315 データシートの表示（PDF） - Maxim Integrated

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MAX9315

1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver

Maxim Integrated 

1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Driver

AC ELECTRICAL CHARACTERISTICS

(VCC - VEE = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20%

to 80%), SEL = high or low, EN = low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or

VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 7)

PARAMETER

SYMBOL CONDITIONS

-40°C

+25°C

+85°C

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX ps

Differential Input-

to-Output Delay

tPLHD,

tPHLD

Figure 2

290

400 310

440 300

520 ps

Output-to-Output

Skew (Note 8)

Part-to-Part Skew

(Note 9)

Added Random

Jitter (Note 10)

tSKOO

tSKPP

tRJ

fIN = 1.5GHz clock

5 30

110

0.8 1.2

20 40

130

0.8 1.2

20 50 ps

220 ps

0.8 1.2 ps (RMS)

Added

Deterministic Jitter

(Note 10)

1.5Gbps 2E23-1

tDJ

PRBS pattern

50 70

50 70

50 70 ps (p-p)

Switching

Frequency

(VOH - VOL) ≥

fMAX 400mV,

1.5

Figure 2

1.5

1.5

GHz

Output Rise/Fall

Time (20% to 80%)

tR, tF Figure 2

80

120 90

130 90

145 ps

Note 1: Measurements are made with the device in thermal equilibrium.

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.

Note 3: DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range.

Note 4: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V.

Note 5: Use VBB only for inputs that are on the same device as the VBB reference.

Note 6: All pins open except VCC and VEE.

Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.

Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition.

Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.

Note 10: Device jitter added to the input signal.

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