56F8323 データシートの表示（PDF） - Motorola => Freescale

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56F8323

16-bit Hybrid Controllers

Motorola => Freescale 

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as

detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row

describes the signal or signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8323

56F8123

Power (VDD or VDDA)

6

6

Power Option Control

1

1

Ground (VSS or VSSA)

5

5

Supply Capacitors1 & VPP2

4

4

PLL and Clock

2

2

Interrupt and Program Control

2

2

Pulse Width Modulator (PWM) Ports3

12

—

Serial Peripheral Interface (SPI) Port 04

4

8

Quadrature Decoder Port 05

4

—

CAN Ports

2

—

Analog-to-Digital Converter (ADC) Ports

13

13

Timer Module Port C6

3

3

Timer Module Port A

—

4

JTAG/Enhanced On-Chip Emulation (EOnCE)

5

5

Temperature Sensse

1

—

Dedicated GPIO

—

10

1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs

2. The VPP input shares the IRQA input

3. Pins in this section can function as SPI #1 and GPIO

4. Pins in this section can function as SCI #1 and GPIO

5. Alternately, can function as Quad Timer A pins or GPIO

6. Two pins can function as SCI #0 and GPIO

Note: See Table 1-1 for 56F8123 functional differences.

56F8323 Technical Data, Rev. 11.0

14

Freescale Semiconductor

Preliminary

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