P80C54SBBB データシートの表示（PDF） - Philips Electronics
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P80C54SBBB Datasheet PDF : 56 Pages
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Philips Semiconductors
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
Interrupt Priority Structure
The 8XC51FA/FB/FC and 8XC51RA+/RB+/RC+/RD+ have a
7-source four-level interrupt structure (see Table 8). The
80C52/54/58 and 80C32 only have a 6-source four-level interrupt
structure because these devices do not have a PCA.
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
IPH.x
IP.x
0
0
0
1
1
0
1
1
INTERRUPT PRIORITY LEVEL
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
Table 8. Interrupt Table
SOURCE
POLLING PRIORITY
X0
1
T0
2
X1
3
T1
4
PCA
5
SP
6
T2
7
NOTES:
1. L = Level activated
2. T = Transition activated
REQUEST BITS
IE0
TF0
IE1
TF1
CF, CCFn
n = 0–4
RI, TI
TF2, EXF2
HARDWARE CLEAR?
N (L)1 Y (T)2
Y
N (L) Y (T)
Y
N
N
N
VECTOR ADDRESS
03H
0B
13
1B
33
23
2B
7
6
5
4
3
2
1
0
IE (0A8H)
EA
EC
ET2
ES
ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
EC
PCA interrupt enable bit for FX and RX+ only – otherwise it is not implemented.
IE.5
ET2
Timer 2 interrupt enable bit.
IE.4
ES
Serial Port interrupt enable bit.
IE.3
ET1
Timer 1 interrupt enable bit.
IE.2
EX1
External interrupt 1 enable bit.
IE.1
ET0
Timer 0 interrupt enable bit.
IE.0
EX0
External interrupt 0 enable bit.
SU00840
Figure 10. IE Registers
1999 Apr 01
22
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