QLX411RIQT7 データシートの表示（PDF） - Intersil

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QLX411RIQT7

Quad Lane Extender

Intersil 

QLx411GRx

CML Input and Output Buffers

The input and output buffers for the high-speed data

channels in the QLx411GRx are implemented using CML.

Equivalent input and output circuits are shown in

Figures 6 and 7.

VDD

IN[k] P

50Ω

Buffer

IN[k] N

50Ω

FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR

THE QLx411GRx

Line Silence/Quiescent Mode

Line silence is commonly broken by the limiting

amplification in other equalizers. This disruption can be

detrimental in many systems that rely on line silence as

part of the protocol. The QLx411GRx contains special

lane management capabilities to detect and preserve

periods of line silence while still providing the fidelity-

enhancing benefits of limiting amplification during active

data transmission. Line silence is detected by measuring

the amplitude of the equalized signal and comparing that

to a threshold set by the voltage at the DT pin. When the

amplitude falls below the threshold, the output driver

stages are muted and held at their nominal common

mode voltage1.

LOS Indicator

Pins LOS[k] are used to output the state of the muting

circuitry to serve as a loss of signal indicator for channel

k. This signal is directly derived from the muting signal

off the DT-threshold signal detector output. The LOS

signal goes HIGH when the power signal is below the DT

threshold and LOW when the power goes above the DT

threshold. This feature is meant to be used in optical

systems (e.g. QSFP) where there are no quiescent or

electrical-idle states. In these cases, the DT threshold is

used to determine the sensitivity of the LOS indicator.

VDD

50Ω

50Ω

OUT[k] P

OUT[k] N

FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR

THE QLx411GRx

1. The output common mode voltage remains constant during both active data transmission and output muting modes

8

FN6989.1

November 19, 2009

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