AD5424YCP データシートの表示（PDF） - Analog Devices
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AD5424YCP Datasheet PDF : 32 Pages
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AD5424/AD5433/AD5445
IOUT1 1
IOUT2 2
20 RFB
19 VREF
GND 3
DB9 4
DB8 5
DB7 6
AD5433
(Not to Scale)
18 VDD
17 R/W
16 CS
15 NC
DB6 7
14 NC
DB5 8
13 DB0 (LSB)
DB4 9
12 DB1
DB3 10
11 DB2
NC = NO CONNECT
Figure 5. AD5433 Pin Configuration (TSSOP)
20 19 18 17 16
GND 1
DB9 2
DB8 3
DB7 4
DB6 5
PIN 1
INDICATOR
AD5433
TOP VIEW
15 R/W
14 CS
13 NC
12 NC
11 DB0
6 7 8 9 10
NC = NO CONNECT
Figure 6 AD5433 Pin Configuration (LFCSP).
Table 5. AD5433 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
19
IOUT1
2
20
IOUT2
3
1
GND
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground.
4–13 2–11 DB9–DB0 Parallel Data Bits 9 to 0.
14, 15 12, 13 NC
Not Internally Connected.
16
14
CS
Chip Select Input. Active low. Use in conjunction with R/W to load parallel data to the input latch or to read data
from the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to read back
contents of DAC register.
18
16
VDD
19
17
VREF
20
18
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
IOUT1 1
IOUT2 2
GND 3
DB11 4
DB10 5
DB9 6
DB8 7
AD5445
(Not to Scale)
20 RFB
19 VREF
18 VDD
17 R/W
16 CS
15 DB0 (LSB)
14 DB1
20 19 18 17 16
GND 1
DB11 2
DB10 3
DB9 4
DB8 5
PIN 1
INDICATOR
AD5445
TOP VIEW
15 R/W
14 CS
13 DB0
12 DB1
11 DB2
DB7 8
13 DB2
6 7 8 9 10
DB6 9
DB5 10
12 DB3
11 DB4
Figure 8. AD5445 Pin Configuration (LFCSP)
Figure 7. AD5445 Pin Configuration (TSSOP)
Table 6. AD5445 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
19
IOUT1
2
20
IOUT2
3
1
GND
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground Pin.
4–15 2–13 DB11–DB0 Parallel Data Bits 11 to 0.
16
14
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from
the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents
of DAC register.
18
16
VDD
19
17
VREF
20
18
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
Rev. B | Page 8 of 32
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