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HD64336086 データシートの表示(PDF) - Renesas Electronics

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HD64336086 Datasheet PDF : 506 Pages
First Prev 491 492 493 494 495 496 497 498 499 500 Next Last
Main Revisions and Additions in this Edition
Item
Preface
Section 6 Power-Down
Modes
6.1.1 System Control
Register 1 (SYSCR1)
Page Revision (See Manual for Details)
vi, vii When using the on-chip emulator (E7, E8) for H8/36087
program development and debugging, the following
restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be
used.
3. Area H'D000 to H'DFFF is used by the E7 or E8, and is
not available to the user.
5. When the E7 or E8 is used, address breaks can be set as
either available to the user or for use by the E7 or E8. If
address breaks are set as being used by the E7 or E8, the
address break control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin
(open-drain in output mode).
7. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in on-
board programming mode by boot mode.
Note has been deleted.
75
Bit Bit Name Description
3 NESEL Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the
watch clock signal (φW) and the system clock
pulse generator generates the oscillator clock
(φOSC). This bit selects the sampling frequency of
the oscillator clock when the watch clock signal
(φW) is sampled. When φOSC = 4 to 18 MHz, clear
NESEL to 0.
Section 8 RAM
107 Note: * When the E7 or E8 is used, area H'F780 to H'FB7F
must not be accessed.
Rev. 2.00 Sep. 23, 2005 Page 465 of 354
REJ09B0160-0200

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