K9K8G08U1M
K9F4G08U0M
Input Data Latch Cycle
CLE
Advance
FLASH MEMORY
tCLH
tCH
CE
ALE
WE
I/Ox
tWC
tALS
tWP
tWH
tDS tDH
DIN 0
tWP
tWP
tDS tDH
DIN 1
tDS tDH
DIN final*
NOTES : DIN final means 2,112
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
CE
RE
I/Ox
R/B
tRC
tREA
tREH
tREA
Dout
tRR
tRHZ
Dout
tREA
tCHZ
tCOH
tRHZ
tRHOH
Dout
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
19