AD842 データシートの表示（PDF） - Analog Devices
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AD842 Datasheet PDF : 10 Pages
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OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which com-
prise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slew-
ing and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
+VS 0.1F
10k⍀
INPUT
–
AD842
+
2.2F
0.1F
OUTPUT
RL
2.2F
–VS
Figure 21. Offset Nulling (DIP Pinout)
AD842
DDD5109
FLAT-TOP
PULSE
GENERATOR
ERROR
AMP
(؋15)
HP6263
499⍀ 1k⍀
499⍀
50⍀
1k⍀
+15V
0.1F
2.2F
499⍀
AD842
0.1F
2.2F
–15V
TEK
7A13
TEK
7A16
TEK
7603
OSCILLOSCOPE
499⍀
FET PROBE
TEK P6201
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD842’s 0.01% set-
tling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed propri-
etary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300 Ω load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
Figure 24 shows the “long term” stability of the settling charac-
teristics of the AD842 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful
layout, avoids these problems by minimizing the effects of tran-
sistor isolation capacitance discharge and thermally induced
shifts in circuit operating points. These problems do not occur
even under high output current conditions.
Figure 22. 0.01% Settling Time
REV. E
–7–
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