AD9779A(2017) データシートの表示（PDF） - Analog Devices
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AD9779A Datasheet PDF : 55 Pages
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AD9776A/AD9778A/AD9779A
Data Sheet
SYNC_O
SYNC_I
DATACLK
P1D[15:0]
DELAY
LINE
DELAY
LINE
DATA
ASSEMBLER
I
LATCH
P2D[15:0]
Q
LATCH
AD9779A
FUNCTIONAL BLOCK DIAGRAM
CLOCK GENERATION/DISTRIBUTION
2×
2×
2×
n × fDAC/8
n = 0, 1, 2 ... 7
2×
2×
2×
CLOCK
MULTIPLIER
2×/4×/8×
SINC^-1
16-BIT
I DAC
SINC^-1
16-BIT
Q DAC
DIGITAL CONTROLLER
SERIAL
PERIPHERAL
INTERFACE
POWER-ON
RESET
10
GAIN
10
GAIN
10
GAIN
10
GAIN
REFCLK+
REFCLK–
OUT1_P
OUT1_N
OUT2_P
OUT2_N
VREF
I120
AUX1_P
AUX1_N
AUX2_P
AUX2_N
Figure 2. AD9779A Functional Block Diagram
Rev. C | Page 4 of 55
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