AD5373 データシートの表示（PDF） - Analog Devices
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AD5373 Datasheet PDF : 28 Pages
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AD5372/AD5373
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
RESET 1
BUSY 2
VOUT27 3
SIGGND3 4
VOUT28 5
VOUT29 6
VOUT30 7
VOUT31 8
NC 9
NC 10
NC 11
NC 12
NC 13
NC 14
NC 15
VDD 16
AD5372/AD5373
TOP VIEW
(Not to Scale)
48 VOUT5
47 VOUT4
46 SIGGND0
45 VOUT3
44 VOUT2
43 VOUT1
42 VOUT0
41 VREF0
40 VOUT23
39 VOUT22
38 VOUT21
37 VOUT20
36 VSS
35 VDD
34 SIGGND2
33 VOUT19
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RESET 1
BUSY 2
VOUT27 3
SIGGND3 4
VOUT28 5
VOUT29 6
VOUT30 7
VOUT31 8
NC 9
NC 10
NC 11
NC 12
NC 13
NC 14
NC 15
VDD 16
PIN 1
INDICATOR
AD5372/AD5373
TOP VIEW
(Not to Scale)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 VOUT5
47 VOUT4
46 SIGGND0
45 VOUT3
44 VOUT2
43 VOUT1
42 VOUT0
41 VREF0
40 VOUT23
39 VOUT22
38 VOUT21
37 VOUT20
36 VSS
35 VDD
34 SIGGND2
33 VOUT19
NOTES
1. NC = NO CONNECT.
2. THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP) HAS AN EXPOSED PAD
ON THE UNDERSIDE. CONNECT THE EXPOSED PAD TO VSS.
Figure 7. 64-Lead LFCSP Pin Configuration
NC = NO CONNECT
Figure 8. 64-Lead LQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
0
EPAD
1
RESET
2
BUSY
42 to 45, 47 to 50, 21 to 24,
26 to 33, 37 to 40, 60 to 62,
3, 5 to 8
4
9 to 15, 19, 20
16, 35
17, 36
18
25
34
41
46
51, 58
52, 57
53
54
55
VOUT0 to
VOUT31
SIGGND3
NC
VDD
VSS
VREF1
SIGGND1
SIGGND2
VREF0
SIGGND0
DGND
DVCC
SYNC
SCLK
SDI
Description
Exposed Pad. The lead frame chip scale package (LFCSP) has an exposed pad on the
underside. Connected the exposed pad to VSS.
Digital Reset Input.
Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and
LDAC Functions section for more information.
DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is
capable of driving an output load of 10 kΩ to ground. Typical output impedance of these
amplifiers is 0.5 Ω.
Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
No Connect.
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be
decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should
be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND.
Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane.
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic
capacitors and 10 μF capacitors.
Active Low Input. This is the frame synchronization signal for the serial interface.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin
operates at clock speeds up to 50 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Rev. C | Page 10 of 28
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