MCP3008T データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

MCP3008T

2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface

Microchip Technology 

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3004/3008 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the

rising edge. Because communication with the

MCP3004/3008 devices may not need multiples of

eight clocks, it will be necessary to provide more clocks

than are required. This is usually done by sending

‘leading zeros’ before the start bit. As an example,

Figure 6-1 and Figure 6-2 shows how the MCP3004/

3008 can be interfaced to a MCU with a hardware SPI

port. Figure 6-1 depicts the operation shown in SPI

Mode 0,0, which requires that the SCLK from the MCU

idles in the ‘low’ state, while Figure 6-2 shows the sim-

ilar case of SPI Mode 1,1, where the clock idles in the

‘high’ state.

MCP3004/3008

As is shown in Figure 6-1, the first byte transmitted to

the A/D converter contains seven leading zeros before

the start bit. Arranging the leading zeros this way

induces the 10 data bits to fall in positions easily

manipulated by the MCU. The MSB is clocked out of

the A/D converter on the falling edge of clock number

14. Once the second eight clocks have been sent to the

device, the MCU receive buffer will contain five

unknown bits (the output is at high-impedance for the

first two clocks), the null bit and the highest order 2 bits

of the conversion. Once the third byte has been sent to

the device, the receive register will contain the lowest

order eight bits of the conversion results. Employing

this method ensures simpler manipulation of the

converted data.

Figure 6-2 shows the same thing in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the A/D converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D converter in on the rising edge of the clock.

CS

SCLK

DIN

MCU latches data from A/D

converter on rising edges of SCLK

1 234 56 78

9 10 11 12 13 14 15 16

Data is clocked out of

A/D converter on falling edges

Start

SGL/

DIFF

D2 D1 DO

17 18 19 20 21 22 23 24

Don’t Care

DOUT

HI-Z

MCU Transmitted Data

(Aligned with falling

edge of clock)

000

0 00

Start

Bit

01

MCU Received Data

(Aligned with rising

edge of clock)

?

?

?

?

?

?

?

?

NULL

BIT

B9

B8

B7 B6 B5 B4 B3 B2 B1 B0

SGL/

DIFF

D2

D1

DO

X

X

XX

?

?

?

?

?

0

(Null)

B9

B8

XXXXX XXX

B7 B6 B5 B4 B3 B2 B1 B0

Data stored into MCU receive

X = “Don’t Care” Bits

register after transmission of first

8 bits

Data stored into MCU receive

register after transmission of

second 8 bits

Data stored into MCU receive

register after transmission of last

8 bits

FIGURE 6-1:

SPI Communication with the MCP3004/3008 using 8-bit segments

(Mode 0,0: SCLK idles low).

© 2008 Microchip Technology Inc.

DS21295D-page 21

Share Link: