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P3041NSE7PNC

P3041 QorIQ Integrated Processor Hardware Specifications

Freescale Semiconductor 

3.3 Power Supply Design

Hardware Design Considerations

3.3.1 PLL Power Supply Filtering

Each of the PLLs described in Section 3.1, “System Clocking,” is provided with power through independent power supply pins

(AVDD_PLAT, AVDD_CCn, AVDD_DDR, and AVDD_SRDSn). AVDD_PLAT, AVDD_CCn, AVDD_DDR voltages must be derived

directly from the SVDD source through a low frequency filter scheme.

The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in

Figure 50, one for each of the AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection

from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to a 10-MHz range.

Each circuit must be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby

circuits. It must be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the footprint,

without the inductance of vias.

The following figure shows the PLL power supply filter circuit.

Where:

R = 5 Ω ± 5%

C1 = 10μF ± 10%, 0603, X5R, with ESL <= 0.5 nH

C2 = 1.0 μF ± 10%, 0402, X5R, with ESL <= 0.5 nH

NOTE

A higher capacitance value for C2 may be used to improve the filter as long as the other C2

parameters do not change (0402 body, X5R, ESL <= 0.5 nH).

Voltage for AVDD is defined at the PLL supply filter and not the pin of AVDD.

R

VDD_CA_CB_PL

C1

AVDD_PLAT, AVDD_CCn, AVDD_DDR

C2

Low ESL surface mount capacitors

GND

Figure 50. PLL Power Supply Filter Circuit

The AVDD_SRDS signals provide power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the

power supplied to the PLL is filtered using a circuit similar to the one shown in the following figure. For maximum

effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as

possible. The ground connection must be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed

by two 2.2-µF capacitors, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn

to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces must be kept short,

wide, and direct.

SVDD

1.0 Ω

2.2 µF1

2.2 µF1

AVDD_SRDSn

0.003 µF

GND

Figure 51. SerDes PLL Power Supply Filter Circuit

P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

141

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